Electrostatic discharge (ESD) is a known cause of failure in metal oxide semiconductor field effect transistors (MOSFETs). In ESD, a relatively large pulse of current which has been acquired from external factors, such as triboelectric charging of a package, flows unintendedly through elements of an integrated circuit (IC) chip. The elements that initially encounter an ESD pulse are typically input and/or output buffers that are directly connected to bond pads or terminals which may be exposed to external events such as an ESD pulse. Such buffers, which are typically relatively large transistors, may be damaged by an ESD pulse, or smaller internal transistors on a chip may be damaged. The current pulse can flow into a transistor from the gate, the drain or the source, although the source is typically connected to a power supply and is unlikely to supply an ESD pulse. An ESD pulse supplied to the transistor through the gate will break down a dielectric gate oxide barrier between the gate and the channel, which may lead to permanent damage by leaving a conductive path of ionized dielectric or trapped electrons, or by burning a hole in the gate oxide.
An ESD current pulse originating at the drain may flow to either the substrate, the gate or the source. Any of these flows may similarly cause permanent damage to the gate oxide. Even if the ESD pulse, which may be several thousand volts, does not flow directly from the drain to the gate, an electronic ripple from this pulse may destroy the gate oxide layer, which may break down at 20 volts or less. The destruction of the gate oxide renders the circuit, chip, and often the device containing the chip dysfunctional.
To improve the speed and other performance characteristics of MOSFETs, especially in response to problems such as parasitic resistances that occur with submicron devices, the formation of silicide layers at the surfaces of sources, gates and drains is commonly employed. These conductive layers of metal and silicon, termed "salicide" when self-aligned, further aggravate the ESD problem, by reducing resistances that had formerly protected the circuit from ESD. In addition, as described in U.S. Pat. No. 4,855,620 to Duvvury et al., the metal of these silicided areas can be melted by heat generated by an ESD event, and flow along electric field lines to cause permanent short circuiting of the device. Similarly, the lightly doped drain (LDD) structure, used to reduce the peak drain electric field of near-micron and submicron N-channel transistors, and in some cases to minimize short channel effects in P-channel transistors, also has been reported to increase vulnerability to ESD.
Several methods for improving the ESD immunity of advanced MOSFET and complementary metal-oxide-silicon (CMOS) devices have been proposed. One approach is to add an additional output protection circuit to protect against ESD, as taught by Duvvury et al. Similarly, in U.S. Pat. No. 4,692,781, Rountree et al. disclose an input protection circuit and an output protection circuit which are added to a transistor for ESD immunity.
Instead of adding circuits, the addition of a large space between the drain metal contact and the gate edge has been proposed as a means to add resistance in series with the drain of the output transistor. In a silicided structure, however, the amount of resistance added is minimal, as is the effect on ESD. "Silicide-blanking" allows the creation of silicon and polysilicon resistors from the source and drain by patterning where the silicidation occurs and does not occur. Lowering the doping and therefore increasing the impedance of the source and drain is another approach to preventing ESD, but is constrained by the degree to which drain and source concentrations can be lowered before affecting device performance. Finally, re-engineering the drain for higher electric fields and lower snapback voltage have been proposed, but this runs counter to the requirements for stable, short channel transistors.
An object of the present invention is to provide a transistor structure that is protected from ESD without an additional circuit or layer of material.
Another object of this invention is to provide a method for making such a transistor that is not appreciably more complicated than prior art methods for making less protected transistors.